Single-ended cascode voltage switch logic and differential cascode voltage switch logic have been extensively discussed in the open literature (see, for example, Carter et al "Cascode Parity Circuit," IBM Technical Disclosure Bulletin, Vol. 24, No. 3, Aug. 1981, pp. 1705-1706; and Hiltebeitel "CMOS XOR," IBM Technical Disclosure Bulletin, Vol 24, No. 11A, Apr. 1982, pp. 5470-5471). Briefly, a typical CVS circuit is partitioned into any number of basic building blocks called logic modules, each including a logic tree, an associated buffer and a precharge circuit. The buffer and precharge circuits are generally identical but the internal structure of the logic trees may be different depending upon which logic function a logic tree is designed to implement.
In a conventional cascode voltage switch circuit, the switching of any single branch within the logic tree results in discharging of the internal node capacitances of all other branches. This "additional" discharging reduces the switching speed of the circuit and limits the number of logic branches within the tree (i.e., the discharging worsens as the "width" of the logic tree increases).
Thus, a need exists for an enhanced cascode voltage switch circuit design wherein the various logic branches of the logic tree are isolated such that there is no unnecessary discharging of inactive branches. The present invention provides such a circuit design.